The invention relates to a method for fabricating a power transistor arrangement and a mask for carrying out the method. Moreover, the invention relates to a power transistor arrangement.
Transistor arrangements fashioned as MOS (Metal Oxide semiconductor) power transistors are provided for controlling switching currents having high current intensities (up to several tens of amperes) by means of low control voltages. The dielectric strength of such power transistors may be as much as several 100 V. The switching times are usually in the region of a few microseconds.
MOS power transistors take the form of trench MOS power transistors, for example. A trench MOS power transistor is formed in a semiconductor substrate having, in at least one active cell array, in each case a plurality of trench transistor cells arranged next to one another.
Depending on the fashioning of the trench transistor cells, it is possible to realize for example normally on and normally off p-channel and n-channel trench MOS power transistors.
FIG. 1 shows a conventional power transistor arrangement 1 embodied as a trench MOS power transistor with a schematic illustration of the source, drain and gate connections, which is embodied as an n-channel MOSFET with a vertical double-diffused trench structure (VDMOSFET, vertical double-diffused metal oxide semiconductor field effect transistor). In this case, a drain metallization 231 connected to the drain connection is arranged on a rear side of a semiconductor substrate 16. An n++-doped drain layer 23 adjoins the drain metallization 231 in the semiconductor substrate 16. A drift zone 232 adjoins the drain layer 23 opposite to the drain metallization 231. The drift zone 232 is generally formed from a weakly n-doped semiconductor substrate 16 that generally comprises silicon applied epitaxially. A space charge zone forms in the drift zone 232 during off-state operation of the trench MOS power transistor, the extent of said space charge zone essentially determining the maximum reverse voltage.
In a cell array 3, cell array trenches 5 are arranged in the semiconductor substrate 16. The cell array trenches 5, which are illustrated in cross section, in this example extend parallel in a direction perpendicular to the cross-sectional area. Gate electrode structures 10 and field electrode structures 11 are arranged in the cell array trenches 5. The field electrode structure 11 is insulated from the semiconductor substrate 16 by an insulation layer 18, which may comprise a field oxide, for example. The gate electrode structure 10 is insulated from the field electrode structure 11 and the semiconductor substrate 16 by a gate insulation layer 20, which may be a silicon oxide, for example. The drift zone 232 of the semiconductor substrate 16 is adjoined by p-doped body zones in regions between the cell array trenches 5, said body zones approximately being situated opposite the gate electrode structures 10. n++-doped source regions 8a are provided between the body zones and a substrate surface 17. The field electrode structures 11 reduce a parasitic capacitance between the gate electrode structures 10 and the drift zone 232. A source metallization 15 is electrically conductively connected to the source regions 8a by means of source contact trenches 8. The source metallization 15 is electrically insulated with respect to the gate electrode structures 10 by an intermediate oxide layer 22. The material both of the gate electrode structures 10 and of the field electrode structures 11 is heavily doped polysilicon, for example. The conductivity of the gate electrode structure 10 may be improved for example by an additional layer in the gate electrode structure 10, for instance a silicide layer. The cell array trench 5 with the gate electrode structure 10 and the field electrode structure 11 forms, together with the adjoining doped regions of the semiconductor substrate 16, a trench transistor cell 2 extending as far as the drain layer 23.
If a positive potential is applied to the gate electrode structure 10 in such an active trench transistor cell 2, then an n-conducting inversion channel forms in the p-doped body zone from the minority carriers (electrons) of the p-doped body zone that have accumulated there.
In an edge region 4 of the power transistor arrangement 1 formed as a trench MOS power transistor, on the one hand the field electrode structures 11 arranged in the cell array trenches 5 are contact-connected to the source metallization 15, and on the other hand the gate electrode structures 10 arranged in the cell array trenches 5 are contact-connected to a gate metallization 14. Furthermore, an example of a shielding electrode 12 is illustrated in the edge region 4.
By way of example, the field electrode structures 11 arranged in the cell array trenches 5 are contact-connected in a cross-sectional plane VII parallel to the cross-sectional plane VI. In the cell array trenches 5, running perpendicular to the cross-sectional plane VI, the gate electrode structures 10 do not extend over the entire length of the cell array trenches 5, so that the respective field electrode structure 11 is contact-connected in a connection region of the cell array trenches 5, as shown in the plane VII. Each field electrode structure 11 pulled over the substrate surface 17 is electrically conductively connected to the source metallization 15. Moreover, a shielding electrode 12 extending above the substrate surface 17 is formed.
In a further cross-sectional plane VIII extending between the first cross-sectional plane VI and the second cross-sectional plane VII parallel thereto, the gate electrode structures 10 are electrically connected to an edge gate structure 13. The edge gate structure 13 is electrically conductively connected to the gate metallization 14. The edge gate structures 13 and the shielding electrodes 12 are generally formed from doped polysilicon. The source metallization 15, the gate metallization 14, the edge gate structure 13, the shielding electrode 12, and also the semiconductor substrate 16 are mutually insulated from one another in each case by an insulation layer 18, an intermediate oxide layer 22 and also a further insulation layer 18.
In order to fabricate a complex structure, such as the power transistor arrangement described in FIG. 1, in which both the gate electrode structure and the field electrode structure are led out into the edge region and connected there in each case to a gate metallization, and a source metallization, respectively, at least five to seven patterning planes are employed in the present-day fabrication methods. A patterning plane generally comprises a lithographic imaging of structures that are predefined on an exposure mask onto the semiconductor substrate to be patterned and subsequent etching, deposition or growth and planarization steps.
The at least seven patterning planes for fabricating a power transistor arrangement such as has been described in FIG. 1, for example, contain a trench patterning, during which cell array and edge trenches are introduced into the semiconductor substrate, a patterning of deposited polysilicon for formation of the field electrode structure, a patterning of a gate insulation layer (gate oxide), a patterning of a second deposited polysilicon layer for formation of the gate electrode structure, a patterning of body and source regions, a patterning of contact holes, and a patterning of a metal plane.
A major cost factor in each patterning plane is the lithographic imaging, since the requisite devices are technically very complicated and cost-intensive. Moreover, the entire imaging process requires a high precision and is thus highly susceptible to error. For the reasons mentioned, it is endeavored to reduce the number of lithographic imagings and thus also the number of patterning planes.
A fabrication method with only five patterning planes has already been proposed. In the method, the body and source patterning and also gate electrode patterning planes are eliminated. Lithographic imagings are then not used any longer either for body patterning, source patterning or for gate electrode patterning. The remaining five patterning planes comprise the trench patterning, the field electrode patterning, the patterning of the gate insulation layer, the contact hole patterning and the patterning of the metal plane.
The present invention is based on the object of providing a cost-effective method with a further reduced number of patterning planes for fabrication of a power transistor arrangement. Moreover, it is an object of the invention to provide a mask for carrying out the method. The object further encompasses a power transistor arrangement fabricated by the method.
This object is achieved by means of a method having the features of patent claim 1 and by means of a mask for carrying out the method in accordance with patent claim 14. Furthermore, the object is achieved by means of a power transistor arrangement in accordance with patent claim 23. Advantageous developments of the invention emerge from the respective subclaims.